Generally, semiconductor devices include a plurality of circuits that form an integrated circuit fabricated on a single substrate, such as a silicon crystal substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device typically requires the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures based on copper. Copper based interconnects are desirable due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the substrate and metal lines run parallel to the substrate. Further enhancement of the speed of signals and reduction of interaction of signals in adjacent copper lines (known as “cross-talk”) can be achieved in new IC product chips by surrounding the copper lines and vias in a low k or ultralow k (ULK) dielectric, having a dielectric constant of about 1.5 to about 3.0. Still further speed enhancement can be achieved using an air gap (AG) structure with the dielectric constant of air=1.0.
Presently, interconnect structures formed on an integrated circuit chip consist of at least about 2 to 10 wiring levels. In one class of structures, a low dielectric constant (k) material having a dielectric constant less than 3.0 is used.
However, reliability problems are often associated with these structures.
During integration, reliability stress, or extended use, a chip interconnect structure made in a ULK dielectric may fail or degrade due to poor liner barrier quality for the metal liner barrier between Cu and the ULK dielectric. This poor quality usually results from defects in the liner barrier, allowing Cu or Cu+ to penetrate the dielectric and allowing oxidizing species (H2O, O2, etc.) to interact with the Cu. The defects and roughness are typically due to uneven coverage during the liner barrier deposition, for example, the presence of pores and roughness on the ULK dielectric can result in small regions where the liner barrier is thin or discontinuous. Also, it may be difficult to deposit the liner barrier at the bottom of high aspect ratio vias, so the thin or discontinuous liner regions commonly are formed at the bottom of said vias, near the interface where the via meets the line below.
Thus, there is a need to reduce or prevent defects in the liner barrier that are caused by open pores and extreme roughness on the surfaces of etched openings.
In addition, interconnect structures for high performance may use an air gap (AG) or air bridge to achieve the lowest dielectric constant.
Reliability problems with these structures also usually involve Cu oxidation, because the metal liner barrier may be too thin to prevent Cu oxidation, or defects may form in the liner barrier during manufacturing due to particulates, lithography defects, or other sources. Also, dielectric breakdown in the AG may occur.
Thus, there is a need in AG structures to improve reliability by adding protection of the Cu against oxidation, and also to prevent dielectric breakdown.